Motorola MC9S12DT128B User Manual

DOCUMENT NUMBER

9S12DT128BDGV1/D

MC9S12DT128B

Device User Guide

V01.07

Covers also

MC9S12DG128B, MC9S12DJ128B,

MC9S12DB128B

Original Release Date: 18 June 2001

Revised: 16 Aug 2002

Motorola, Inc

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or

design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;

neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,

or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was

negligent regarding the design or manufacture of the part.

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Table of Contents

Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Section 2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 7

2.1

Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .53

PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . . . .54

PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . . . .54

PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . . . .54

PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .54

2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .54

2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4

2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.18 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

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2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .5 8

2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . .58

2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . .59

2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . .59

2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . .59

2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 0

2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.49 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.50 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.52 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.53 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.54 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.55 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.3.56 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.4

Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

VDDX,VSSX — Power & Ground Pins for I/O Driver s . . . . . . . . . . . . . . . . . . . . . . . .6 2

VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator

VDD1, VDD2, VSS1, VSS2 — Core Power Pin s . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2

VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .63

VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .63

VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .63

VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Section 3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5

3.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Section 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 7

4.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Section 5 Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1

5.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Section 6 HCS12 Core Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5

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Section 7 Clock and Reset Generator (CRG) Block Description . . . . . . . . .7 5

7.1

Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

7.1.1

Section 8 Enhanced Capture Timer (ECT) Block Description. . . . . . . . . . . .75

Section 9 Analog to Digital Converter (ATD) Block Description. . . . . . . . . .75

Section 10 Inter-IC Bus (IIC) Block Description . . . . . . . . . . . . . . . . . . . . . . .75

Section 11 Serial Communications Interface (SCI) Block Description. . . . .75

Section 12 Serial Peripheral Interface (SPI) Block Description . . . . . . . . . .76

Section 13 J1850 (BDLC) Block Description. . . . . . . . . . . . . . . . . . . . . . . . . .76

Section 14 Byteflight (BF) Block Description . . . . . . . . . . . . . . . . . . . . . . . . .76

Section 15 Pulse Width Modulator (PWM) Block Description. . . . . . . . . . . .76

Section 16 Flash EEPROM 128K Block Description . . . . . . . . . . . . . . . . . . .76

Section 17 EEPROM 2K Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . .76

Section 18 RAM Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Section 19 MSCAN Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Section 20 Port Integration Module (PIM) Block Description . . . . . . . . . . . .77

Section 21 Voltage Regulator (VREG) Block Description . . . . . . . . . . . . . . .77

Section 22 Printed Circuit Board Layout Proposal . . . . . . . . . . . . . . . . . . . .78

Appendix A Electrical Characteristics

A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

A.1.1

A.1.2

Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

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Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

ESD Protection and Latch-up Immunit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

A.2.1

A.2.2

A.2.3

ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

A.3.1

A.3.2

NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

A.5.1

A.5.2

A.5.3

Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

A.7.1

A.7.2

Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Appendix B Package Information

B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

B.3 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

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List of Figures

Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 1-1 MC9S12DT128B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 1-2 MC9S12DT128B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B,

MC9S12DJ128B, MC9S12DB128B48

Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128B, MC9S12DJ128B Bondout . .49

Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 2-4 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 2-5 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 2-6 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .79

Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .80

Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .81

Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .82

Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure A-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure A-3 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure A-4 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 22-5 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . .120

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List of Tables

Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

$0000 - $000F MEBI map 1 of 3 (Core User Guide) ........................................................22

$0010 - $0014 MMC map 1 of 4 (Core User Guide) ........................................................22

$0015 - $0016 INT map 1 of 2 (Core User Guide) ...........................................................23

$0017 - $0017 MMC map 2 of 4 (Core User Guide) ........................................................23

$0018 - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3) ....................23

$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4 ) ...................23

$001E - $001E MEBI map 2 of 3 (Core User Guide) ........................................................23

$001F - $001F INT map 2 of 2 (Core User Guide) ...........................................................23

$0020 - $0027 Reserved ..................................................................................................24

$0028 - $002F BKP (Core User Guide) ...........................................................................24

$0030 - $0031 MMC map 4 of 4 (Core User Guide) ........................................................24

$0032 - $0033 MEBI map 3 of 3 (Core User Guide) ........................................................24

$0034 - $003F CRG (Clock and Reset Generator) ..........................................................25

$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................25

$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................28

$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................29

$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................31

$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................31

$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................32

$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................32

$00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ........................................33

$00F0 - $00F7 SPI1 (Serial Peripheral Interface) ............................................................33

$00F8 - $00FF Reserved ..................................................................................................33

$0100 - $010F Flash Control Register (fts128k2) ............................................................34

$0110 - $011B EEPROM Control Register (eets2k) ........................................................34

$011C - $011F Reserved for RAM Control Register ........................................................35

$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................35

$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..............................................36

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .37

$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ..............................................38

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$01C0 - $01FF Reserved ..................................................................................................39

$0200 - $023F Reserved ..................................................................................................39

$0240 - $027F PIM (Port Integration Module) ..................................................................40

$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ..............................................42

$02C0 - $02FF Reserved ..................................................................................................43

$0300 - $035F Byteflight ..................................................................................................43

$0360 - $03FF Reserved ..................................................................................................45

Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 2-2 MC9S12DT128B Power and Ground Connection Summar y . . . . . . . . . . . . . . . . .6 1

Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table A-3 ESD and Latch-Up Protection Characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 6

Table A-4 Operating Condition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table A-10 ATD Conversion Performanc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5

Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Table A-13 Voltage Regulator Recommended Load Capacitance s . . . . . . . . . . . . . . . . . . . .1 01

Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

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Preface

The Device User Guide provides information about the MC9S12DT128B device made up of standard

HCS12 blocks and the HCS12 processor core.

This document is part of the customer documentation. A complete set of device manuals also includes the

HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort

to reduce redundancy all module specific information is located only in the respective Block User Guide.

If applicable, special implementation details of the module are given in the block description sections of

this document.

This document also covers the MC9S12DG128B, MC9S12DJ128B and MC9S12DB128B.

Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the

compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.

Table 0-1 Derivative Differences

Modules

# of CANs

CAN4

MC9S12DT128B MC9S12DG128B MC9S12DJ128B MC9S12DB128B

✓

CAN1

✓

CAN0

✓

J1850/BDLC

IIC

✓

Byteﬂight

Package

112 LQFP

112 LQFP/80 QFP 112 LQFP/80 QFP

112 LQFP

Package

Code

PV/FU

Mask set

L85D

Temp Options

M, V, C

An errata exists

contact Sales

Ofﬁce

An errata exists

contact Sales

Ofﬁce

An errata exists

contact Sales

Ofﬁce

An errata exists

contact Sales

Ofﬁce

Notes

NOTES:

1. ✓: Available for this device, ✕: Not available for this device

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The following figure provides an ordering number example for the MC9S12D128B devices.

MC9S12 DJ128B C FU

Temperature Options

Package Option

Temperature Option

Device Title

C = -40˚C to 85˚C

V = -40˚C to 105˚C

M = -40˚C to 125˚C

Package Options

FU = 80QFP

PV = 112LQFP

Controller Family

Figure 0-1 Order Partnumber Example

See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.

Table 0-2 Document References

User Guide

Version

Document Order Number

HCS12COREUG

S12CRGV3/D

HCS12_V1.5 Core User Guide

1.2

Clock and Reset Generator (CRG) Block User Guide

Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide

Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide

Inter IC Bus (IIC) Block User Guide

V03

V01

V02

V01

V02

V01

S12ECT16B8CV1/D

S12ATD10B8CV2/D

S12IICV2/D

Asynchronous Serial Interface (SCI) Block User Guide

Serial Peripheral Interface (SPI) Block User Guide

S12SCIV2/D

S12SPIV2/D

Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide

128K Byte Flash (FTS128K) Block User Guide

S12PWM8B8CV1/D

S12FTS128KV1/D

S12EETS2KV1/D

S12BDLCV1/D

2K Byte EEPROM (EETS2K) Block User Guide

Byte Level Data Link Controller -J1850 (BDLC) Block User Guide

Motorola Scalable CAN (MSCAN) Block User Guide

Voltage Regulator (VREG) Block User Guide

S12MSCANV2/D

S12VREGV1/D

Port Integration Module (PIM_9DT128) Block User Guide

Byteflight (BF) Block User Guide

S12PIMDT128V1/D

S12BFV1/D

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Section 1 Introduction

1.1 Overview

The MC9S12DT128B microcontroller unit (MCU) is a 16-bit device composed of standard on-chip

peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K

bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two

serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit

analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link

Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital

I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules

(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128B has full 16-bit data paths

throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory

can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and

performance to be adjusted to suit operational requirements.

1.2 Features

•

HCS12 Core

– 16-bit HCS12 CPU

i. Upward compatible with M68HC11 instruction set

ii. Interrupt stacking and programmer’s model identical to M68HC11

iii.20-bit ALU

iv. Instruction queue

v. Enhanced indexed addressing

– MEBI (Multiplexed External Bus Interface)

– MMC (Module Mapping Control)

– INT (Interrupt control)

– BKP (Breakpoints)

– BDM (Background Debug Mode)

CRG (Clock and Reset Generator)

– Choice of low current Colpitts oscillator or standard Pierce Oscillator

– PLL

•

– COP watchdog

– real time interrupt

– clock monitor

•

8-bit and 4-bit ports with interrupt functionality

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– Digital filtering

– Programmable rising or falling edge trigger

•

Memory

– 128K Flash EEPROM

– 2K byte EEPROM

– 8K byte RAM

•

Two 8-channel Analog-to-Digital Converters

– 10-bit resolution

– External conversion trigger capability

Three 1M bit per second, CAN 2.0 A, B software compatible modules

– Five receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– Loop-back for self test operation

Enhanced Capture Timer

•

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels

– Two 8-bit or one 16-bit pulse accumulators

8 PWM channels

– Programmable period and duty cycle

– 8-bit 8-channel or 16-bit 4-channel

– Separate control for each pulse width and duty cycle

– Center-aligned or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

– Fast emergency shutdown input

– Usable as interrupt inputs

•

Serial interfaces

– Two asynchronous Serial Communications Interfaces (SCI)

– Two Synchronous Serial Peripheral Interface (SPI)

– Byteflight

•

Byte Data Link Controller (BDLC)

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•

SAE J1850 Class B Data Communications Network Interface

– Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in

Automotive Applications

Inter-IC Bus (IIC)

– Compatible with I2C Bus standard

– Multi-master operation

– Software programmable for one of 256 different serial clock frequencies

112-Pin LQFP and 80-Pin QFP package options

– I/O lines with 5V input and drive capability

– 5V A/D converter inputs

•

– Operation at 50MHz equivalent to 25MHz Bus Speed

– Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

1.3 Modes of Operation

User modes

•

Normal and Emulation Operating Modes

– Normal Single-Chip Mode

– Normal Expanded Wide Mode

– Normal Expanded Narrow Mode

– Emulation Expanded Wide Mode

– Emulation Expanded Narrow Mode

Special Operating Modes

•

– Special Single-Chip Mode with active Background Debug Mode

– Special Test Mode (Motorola use only)

– Special Peripheral Mode (Motorola use only)

Low power modes

•

Stop Mode

Pseudo Stop Mode

Wait Mode

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1.4 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12DT128B device.

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Figure 1-1 MC9S12DT128B Block Diagram